The present invention relates to solid-state imaging apparatus, and more particularly relates to solid-state imaging apparatus using an amplified MOS sensor.
In recent years, solid-state imaging apparatus using an amplifier type MOS sensor as the solid-state imaging device are used as power-saving type solid-state imaging apparatus for mobile equipment and are also mounted on high-resolution electronic still cameras. While a progressive scanning where pixel signals are read out in a well regulated sequence is generally used in the current solid-state imaging apparatus using an amplified MOS sensor, it is also required to rapidly read pixel signals of relatively low resolution for example as a small image frame for use in a viewfinder or monitor in those solid-state imaging apparatus to be mounted on the electronic still cameras. For this reason, there has been proposed a processing method where pixel signals in a horizontal or vertical direction are mixed within the solid-state imaging apparatus to reduce the number of image data.
FIG. 1 is a circuit diagram showing construction of a previously proposed solid-state imaging apparatus as disclosed in Japanese Patent Application Laid-Open 2002-330349 where an example is shown of solid-state imaging apparatus having a means for mixing pixel signals in a horizontal direction. The solid-state imaging apparatus includes: a pixel section 1 where unit pixels P11 to P44 are disposed two-dimensionally in rows and columns, here in a 4×4 pixel array; a vertical scanning circuit 2 for selecting a row to be read out of the pixel section 1; a current supplying section 3 for supplying bias current to the pixel section 1; a noise suppressing section 4 for suppressing noise components contained in the output signals of the pixel section 1; a horizontal select switch section 5 for outputting noise-suppressed signals; a horizontal scanning circuit 6 for selecting a column to be read out of the horizontal select switch section 5; and an output line 7.
The unit pixels P11 to P44 each include: a photodiode PD1 serving as a photoelectric conversion section; a reset transistor M1 for resetting detection signal of photodiode PD1; an amplifying transistor M2 for amplifying signals of the photodiode PD1; and a row select transistor M3 for selecting the unit pixels in each row.
A row to be read out of the pixel section 1 is then selected by means of power and signals to be applied on a power supply line VR1 to VR4, row reset line φRST1 to φRST4, and row select line φROW1 to φROW4 that are the outputs of the vertical scanning circuit 2, thereby the pixel signals of the unit pixels P11 to P44 are read out row by row.
At the noise suppressing section 4, a noise suppressing circuit CDS1 to CDS4 consisting of a sampling transistor M21 to M24, holding capacitor C21 to C24, input buffer amplifier A21 to A24, clamping transistor M31 to M34, clamping capacitor C31 to C34, and output buffer amplifier A31 to A34 is respectively provided for each column. The noise suppressing section 4 is constructed by further providing horizontal mixing transistors M41 and M43 to be controlled by horizontal mixing control line φAV−H to which clamp output lines CL11, CL12 and CL13, CL14 are respectively connected.
At each noise suppressing circuit CDS1 to CDS4, the drain of sampling transistor M21 to M24 is connected to respective vertical signal line V11 to V14, the source thereof to one end of the holding capacitor C21 to C24 and to an input end of the input buffer amplifier A21 to A24, and the gate thereof is connected in common to a sampling control line φSH. The output end of the input buffer amplifier A21 to A24 is connected to one end of the clamping capacitor C31 to C34. The other end of the holding capacitor C21 to C24 and the drain of the clamping transistor M31 to M34 are connected in common to a reference voltage line REF, and the source of the clamping transistor M31 to M34 is connected to the other end of the clamping capacitor C31 to C34 and to an input end of the output buffer amplifier A31 to A34, i.e., to clamp output line CL11 to CL14. The gate of the clamping transistor M31 to M34 is connected in common to a clamp control line φCL.
FIG. 2 is an outlined drive timing chart for explaining operation at the time of horizontal mixing in the above described prior-art example. Here a description will be given with noticing operation of the first and second columns from left when the upper first row of the pixel section 1 is selected by the vertical scanning circuit 2. First, the power line VR1 is driven to VR1=H and row select line φROW1 to φROW1=H so as to turn ON the row select transistors M3 of the unit pixels P11 and P12. The signal voltages of photodiodes PD1 contained in the unit pixels P11 and P12 are thereby outputted to the vertical signal lines V11 and V12 through the amplifying transistors M2. The signal voltages on the vertical signal lines V11 and V12 at this time are referred to as VV11-SIG and VV12-SIG.
Here, by driving the sampling control line φSH to φSH=H and clamp control line φCL to φCL=H at the noise suppressing section 4, the sampling transistors M21 and M22 and clamping transistors M31 and M32 are turned ON. The clamp output lines CL11 and CL12 are thereby set to a voltage value VREF of the reference voltage line REF so that difference voltages shown in the following formulas (1), (2) are accumulated at the clamping capacitors C31 and C32.Difference voltage accumulated at C31:VV11-SIGVREF  (1)Difference voltage accumulated at C32:VV12-SIG−VREF  (2)where input buffer amplifiers A21 and A22 each are an amplifier having ideal gain=1.
Next, the clamp control line φCL is changed to φCL=L so as to bring the clamp output lines CL11 and CL12 into their high-impedance status, and then, after driving the row reset line φRST1 to φRST1=H, the condition of φRST1=L is attained again. The reset voltages of photodiodes PD1 contained in the unit pixel P11 and P12 are thereby outputted to the vertical signal line V11 and V12 through the amplifying transistors M2. At this time, supposing the reset voltages on the vertical signal lines V11 and V12 as VV11-RST and VV12-RST and supposing the difference voltages between the signal voltages of the vertical signal lines V11 and V12 and the reset voltage as ΔVV11 and ΔVV12, since the difference voltages occurring at the two ends of the clamping capacitors C31 and C32 are retained due to the fact that the clamp output lines CL11 and CL12 are in their high-impedance status, outputs corresponding to the difference voltages between the signal voltage and reset voltage shown in the following formulas (3) to (6) are obtained at the clamp output line voltages VCL11 and VCL12.ΔVV11=VV11-RST−VV11-SIG  (3)ΔVV12=VV12-RST−VV12-SIG  (4)VCL11=VREF+ΔVV11  (5)VCL12=VREFΔVV12  (6)
Here, even when the thresholds of the amplifying transistors M2 contained in the unit pixels P11 and P12 are different from each other due to the manufacturing variance, since the threshold component is contained in both the signal voltage and reset voltage, an output with canceling variance in the threshold of the amplifying transistors M2 can be attained by obtaining the difference voltage between these. Subsequently, the pixel section 1 and the noise suppressing section 4 are disconnected from each other by changing the sampling control line φSH to φSH=L so as to turn OFF the sampling transistors M21 and M22, and next, the unit pixels P11, P12 and the vertical signal lines V11, V12 are disconnected by changing the row select line φROW1 to φROW1=L.
In continuation, by driving the horizontal mixing control line φAV−H to φAV−H=H to turn ON the horizontal mixing transistor M41, the clamp output lines CL11 and CL12 are connected to each other so that pixel signals of the unit pixels P11 and P12 after noise suppression are mixed along the horizontal direction. The clamp output line voltage VCL11(=VCL12) after the horizontal mixing is expressed as in the following formula (7).VCL11VREF+{(ΔVV11+ΔVV12)/2}  (7)where the clamping capacitors C31 and C32 are supposed to have the same capacitance value CCL.
Similarly, the pixel signals of the unit pixels P13 and P14 after noise suppression are mixed in the horizontal direction. These horizontally mixed signals are sequentially outputted onto the output line 7 with skipping every other column through the horizontal select switch section 5 to be controlled by the horizontal scanning circuit 6 via the output amplifiers A31 to A34. The number of image data is thereby reduced to half.